Template:CheahaTflops

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Revision as of 18:32, 26 June 2015 by Jpr@uab.edu (talk | contribs) (correct flops/cycle for sandy bridge (gen4 and gen5))
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Generation Type Nodes CPUs per Node Cores Per CPU Total Cores Clock Speed (GHz) Instructions Per Cycle Hardware Reference
Gen 2 Intel Xeon E5450 24 2 4 192 3.00 4 Intel Xeon E5450
Gen 3 Intel Xeon X5650 48 2 6 576 2.66 4 Intel Xeon E6550
Gen 4 Intel Xeon E5-2680 3 2 8 48 2.70 8 Intel Xeon E2680
Gen 5 Intel Xeon E5-2650 12 2 8 192 2.00 8 Intel Xeon E2650 (Nodes dedicated to OpenStack+Ceph with 10Gbs network)
Theoretical Peak Flops = (number of cores) * (clock speed) * (instructions per cycle)
Generation Theoretical Peak Tera-FLOPS
Gen 2 2.304
Gen 3 6.129
Gen 4 1.036
Gen 5 3.072
Total TFLOPS 12.541